Test procedures for the WideX

The multiplexed nature of the WideX will make difficult the traditional fault detection method based on visual interferometer results. For example if a chip goes wrong, only 1/16th of the amplitude of one baseline will be affected, and this can remain unseen for quite a while. An automated test procedure is recommended to assess the good health of the machine. This one consists of successively running nested test loops that penetrate deeper and deeper in the system, starting in the computer, and progressing oppositely to the signal flow.

These tests are applied on all 16 cards simultaneously.
4.1 Static test

All the chips inputs are internally set to XY pairs of static values (2 out of the possible 16). One gives a permanent 0 and the other gives a permanent 6 on all multipliers. After one integration period, all the integrators should return the same value, according to the multiplier table and the static value of the pair submitted. This test covers the adder and readout system at real speed, and the static behaviour of the shifters. It is not affected by potential board timing problems.

4.2 Dynamic test

The chips are normally connected to the data present on the backplane (this mode needs to be activated for further testing). The chips are configured in autocorrelation. In AUTO mode, there are 8 possible ACF results and 28 available chips . Every ACF can be found on 3 or 4 different chips. The test consists of verifying that the group of chips that are connected to the same inputs actually produce the same ACF pattern. If only one chip is faulty, it can be located. This test is valid on any type of input signal, but noise source is to be preferred. This test can detect timing errors on the backplane transmission.

See the user interface for this test.

These tests are applied on all 8 cards simultaneously.
5.1 Magnitude OFF

When this bit is activated, all the samples delivered to the backplane have their magnitude bit equal to 0. This causes all channels to produce the bias value.

5.2 Sequence

When this bit is activated, a test signal generator emulates the data from the sampling heads with deterministic data. This sequence can be seqA or seqB, depending on the SEQA/B bit value.

5.2.a Sequence A consists of connecting the 16 sample register from the Sherif to fixed "0" or "1" values so as to implement the following pattern:

The correlation function will be sinewave-like with an 8-channel periodicity, either in AUTO or CROSS mode. This test covers the data drivers layers and the backplane transmission , but is unsensitive to delay value, since a one step delay step is exactly 16 samples, or two periods.

5.2.b Sequence B consists of connecting all 16 samples of this register to the same value and slowly scrolling the 4 possible values so as to get a large sawtooth correlation function of 1 or 2 cycles (TBD) across the 2048 correlation channels. The position of the sawtooth will change by 16 channels every time the delay value is changed by one step. For each sampler the whole delay range has to be scanned. This tests covers the Write Pointer circuitry and the proper synchronization of the 8 delay cards.