The PLL clock generates 8 copies of the 4 GHz and the 250 MHz sinewaves. For the disciplining circuits to work, an accurate relationship of the two signals is requested. To correct for slight  errors in the external cables a tuning point (Johanson trimmer) is installed in every SHERIF which adjusts the 250 MHz ref phase. After tuning, the "adj"  switch should be in the released position. Then  the 8 dataflows from the 8 SHERIFs  should deliver signals not more distant than one 4 GHz cycle, or 250 ps. The purpose of the DELAY coding wheel is to shift the clock of the FPGAs so they can all comfortably catch the data  from the SHERIFs. Then all the 8 FPGAs should  deliver their output streams (512 signals) at the same time.All the backplane transit times from sampler to correlator boards are equal. In practice there are deviations but they are kept sufficiently small so that  all the leading correlator chips can catch the data at the same time. The CORREL coding wheel adjusts the correlator chips clock to the best operating point.