Fig.2 same conditions as fig.1, but
with reduced
loop BW
This instrument, like many others, is
sensitive to the amplitude of the external 10 MHz delivered. If
the amplitude
is lowered to 0 dBm, the noise increases significantly. (See fig.3,
which directly compares to fig.1)
Fig.3 same as fig.1, but with reduced
10 MHz amplitude
A few spurious lines are present, all within specification
<60
dBc. See below.
Fig.4
Big line at 102 kHz offset.
The phase noise is good, with -113dBc/Hz @ 5kHz offset, at 6.8 GHz.
Curiously, in the ~500Hz offset range, it is better when running on the
internal crystal than on the external. Fig.5 shows when in lock (green)
and with 10 MHz BNC removed (red).That means that the 10 MHz PLL
adds phase noise in that range. Probably a lower integrated PN could be
obtained by substituting the external 10 MHz to the internal, if this
is feasible.
Fig.
5 Ext 10 MHz (green) vs. int (red)