Fast electronics experimentation with DiFER  (*)  
     MT, Aug 2009 rev Sept 2010

Short-term goal :
Investigate a "digital front-end" for the 5th generation of  backends of both PdB and PV, based on a 5-bit  fast ADC and a Stratix IV GX Altera  FPGA.

The first milestone consists in having the two chips working together on a single board in a 64-channel  Overlapping Polyphase Filter Bank implemention, at the minimum clock frequency of 8 GHz . Although the chipset should  reach 16 GHz, the speed of 8 GHz is chosen for the initial test, in order to mitigate the two difficulties of the design, one being of digital nature, i.e. proper configuration of both chips, data transmission protocol ...etc, and the second being technological, coming from the large number of  signals requiring picosecond timing accuracies.
The OvPFB functionality will be verified by scanning the channels with a complex total power detector  . 

Hardware setup
A  standalone board containing a 12V power supply and  a  commercial (NI) parallel I/O interface for monitor & control.
Dedicated  Windows  PC ( connected to the network ?  ) running Labview
The setup will be installed on the lab central table, together with generators, etc ... .
Control and Monitor
A Labview GUI allows to configure the ADC registers via SPI and read out the PGA via parallel I/O bus. The 64 channels are sequentially polled and and directed to a single complex total power detector.The quantity of data to read out is  64 x16 bits every 0.5 second or faster, to be displayed on a 64-bar graph.
The sequencing shortens the effective integration time and  makes the total power measurement  noiser than radiometric . Five milliseconds  give a 0.2%  fluctuation, this allows to explore the filters down to 27 dB.  If needed, more can be obtained on one channel by stopping the cycling and then performing software-integration.
When cycling is  stopped on any desired channel , the corresponding complex stream @125 Ms/s is placed on a connector for further processing  (TBD).
Long term goal :  (the one for which the whole thing is worth doing)

Use this design as a building block for a high resolution, multi-window spectrometer (e.g. 64)  for PdB. Every channel of the OvPFB can feed either a FPGA FX or ASIC XF, depending on economic considerations and antenna number at the time of construction. The overlappping design requires the upper half of the frequency channels to be discarded, this is the price for a seamless, non-aliased concatenation of the subbands.
The coarse delay will be performed on the 64 slow data streams by write/read in RAMs , and the fine delay  by barrel-shifting the 125 ps samples.
The output of the digital FrontEnd is a number of slow speed streams (e.g.16) representing  the antenna signal in the selected  frequency windows, with all delays removed. These streams can be later placed on a backplane for baseline- related operations, and also for wideband VLBI phased array summation.

Above :Block diagram of the first prototype
Below : prototype implementation

This prototype will be used to acquire experience about the chips and to deal with the large amount of fast signals that they produce.
When  this degree will be passed, a second board will be undertook (diagram below), incorporating new features that will ease the integration of the  future large system.

(*)   DiFER stands for
  "Digital Front  End  R ......"   
where letter "R" meaning is left as an open parameter that anyone can define according to the tribe he belongs to

a few examples :    (non limitative)

 Revolution ( for IRAM)
 Readiness  (for the NOEMA sponsors)
 Recreation  ( for the BE group)
 Re-creation (for RADIONET)
 Rover ( for the skeptics)
 Revelation ( for the conservative)
 Reconnaissance ( for the airmen)
 Recommendation  (for the SAC)