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In January 2007 the project described below  has been resized in order to accomodate an hypothetical couple of new antennas on the interferometer. Concomitently the frequency resolution was requested to be doubled. This additional load in terms of multiplications per second (thus power dissipation) is a  factor of 3.73 

The whole system has been re-drawn and is now described on  http://www.iram.fr/IRAMFR/TA/backend/WideX/

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Main technical features of the PdB wideband correlator
   Draft document,  M.T. Aug, 2005






The correlator uses bandpass sampling on input analog signals ranging from 2 to 4 GHz. These are provided by the IF processor and the optical IF optical transmission system.

The drawing below represents a convenient implementation of the system. It assumes that a 1000-channel, 250 MHz correlator chip can dissipate less than 3 watts. For higher dissipations, forced air cooling might be adopted.




The correlator will be installed in the present temporary storage zone that can be seen below :


future system

The ceiling aspiration duct which is presenly  obturated will be used to pump out the exhaust of the correlator. Depending on the total power dissipation (TBD), the units may be fed directly with cool air from the floor.



Sampling heads

The 2-4 Ghz bands are digitized at 4 Gsp/s by the SHERIF module. No antialiasing filter is required, as the bands are already conditioned by the IF processor. The 4 GHz frequency and the 250 MHz frequency need an accurate relative timing so they are distributed via coaxial cables on the front panel.

The signal level is adjusted to the proper V/sigma by means of a built-in digital attenuator. The three comparator outputs are encoded and delivered to the demultiplexers. Unfortunately the commercial demux chips come with a built-in /16 counter and all 12 (6x2 bit) need to be disciplined (see PDF on this method) on the master 250 MHz clock.  A packet of 16 (2-bit) samples  is delivered every 4 ns to the delay board RAM.


Delay boards

The delay board acts as a motherboard for the sampling heads. It hosts the RAM layers, the pointer FPGA's, and the backplane data drivers.
For testability, all the circuitry except the data drivers is clocked by the 250 MHz from the front panel, which is repeated to the board by the sampling head. The data drivers are clocked by the backplane clock distribution.
The  data format conversion system records the data at 4Ghz and plays it at 250 Mhz on 16 hardware physical players (see presentation). Embedded in this time-multiplexing system is a digital "delay line" which has a range of a few (TBD, depending on packet size) tens of microseconds, and a resolution of 16 samples, or 4 nanoseconds. Finer resolution is obtained by software processing.

Backplane

All the connections of the backplane are  point-to-point. Connections are impedance-matched lines carrying LVDS at 250 MHz. The clock signal is fanned out by multiple output buffers (one per client board, total 16+6)) located on the backplane.
Each delay board has a 16-sample, two bits per sample, two lines per bit output (64 pins).
Each correlator board processes one sample and has 6 inputs, two bits per input, two lines per bit ( 24 pins).
Note that 64x6=24x16 so there is exactly one data input per data output.




Correlator board

Largely TBD, depending on the possible chip capacity. Every board processes the 15 baselines on one sample . Every chip has  built-in clocked repeaters for data and control signals, so point-to-point distribution is preserved within the board. There are 3 rows of 5 chips. The timing continuously shifts along the rows, from the connector to the end of the board. It is constant across the columns.
The integrators can be  read out serially at 62.5 Mb/sec. The total dump time is 3 to 6 msec per board.








Processing tasks performed by the software
Each correlator unit will be connected to some kind of computer (all interfaces are TBD) for real-time operation.

1/ Configuration
Every second the Dual LO2 module is set to stop the residual fringe rate of both 2 GHz subbands. (see manual (PDF))
Every second the coarse delay is sent to the delay boards via a Monitor & Control bus (TBD). The same bus is used to tweak the samplers by means of 4-bit 16dB step attenuator, and to read the digital total power detectors.

2/ Readout and small delay system
The new subband width (2GHz) and baseline length (1km) make that the basic period during which the correlation can be assumed to be stable for integration is 31.25msec. During this period :

The raw correlations are transmitted from the correlator chips via a serial bus (TBD). There are 16 (or 12 ?...TBD) bits per channel,1024 channels per chip, 15 chips  per board, and 16 boards per chassis. Preferably there should be one serial bus per board. The data from the boards are concentrated in the unit,formatted and sent to the computer via a fast serial link (TBD). This is an average data rate of 125 Mbits/sec.

In the computer, and for each baseline:
-The corresponding channels emanating from the 16 boards are summed to form a 1024 point x 20-bit (16 ?) cross-correlation function.
-The Van Vleck correction is applied.
-The Fourier transform is applied.
-The fractional delay linear slope is applied. Since the hardware can only deal with packets of 16 samples, the range has to be  +/- 8 samples or -2ns...+2ns. The minimum resolution is 31ps or1/8th sample.
-The data is integrated in one of  4 buffers, according to the Walsh function value for that sequence (TBD).

3/ Storage
Every second (TBD) the data is transmitted to further software layers.